Triple Modular Redundancy verification via heuristic netlist analysis

SEUs Mitigation on Program Counter of the LEON3 Soft Processor

Analyzing and evaluating the sensitivity of embedded systems to soft-errors have always been a challenge for aerospace or safety equipment designer. Different automated fault-injection methods have been developed for evaluating the sensitivity of integrated circuit. Also many techniques have been developed to get a fault tolerant architecture in order to mask and mitigate fault injection in a c...

A Fast Heuristic Algorithm for Redundancy Removal

Redundancy identification is an important step of the design flow that typically follows logic synthesis and optimization. In addition to reducing circuit area, power consumption, and delay, redundancy removal also improves testability. All commercially available synthesis tools include a redundancy removal engine which is often run multiple times on the same netlist during optimization. This p...

Analysis of Single-Event Upset Rates in Triple-Modular Redundancy Devices

Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy

Triple Modular Redundancy is widely used in dependable systems design to ensure high reliability against soft errors. Conventional TMR is effective in protecting sequential circuits but can’t mask soft errors in combinational circuits. A new redundancy technique called the Space-Time Triple Modular Redundancy is presented in this paper, which improves the soft error tolerance of the combination...

Hierarchical Triple-Modular Redundancy (H-TMR) Network For Digital Systems

Hierarchical application of Triple-Modular Redundancy (TMR) increases fault tolerance of digital Integrated Circuit (IC). In this paper, a simple probabilistic model was proposed for analysis of fault masking performance of hierarchical TMR networks. Performance improvements obtained by second order TMR network were theoretically compared with first order TMR network.